A Richardson-Lucy Algorithm Based Blind Deconvolution to Decouple the Two Unknown Spatial-Temporal SRAM Margin Variations Reviewed

Hiroyuki Yamauchi and Worawit Sohma

Journal of Physics: Conference Series   2444 ( 1 )   1 - 8   2023.2

Relaxed Training Procedure for a Binary Neural Network Reviewed

Jiazhen Xi and Hiroyuki Yamauchi

International Journal of Machine Learning and Computing   13 ( 1 )   1 - 8   2023.1

A Machine Learning Based Fuel Consumption Saving Method with Time and Environment Dependency Aware Management Reviewed

Peng Yu and Hiroyuki Yamauchi

ACM Digital Library (ISBN: 978-1-4503-9584-7)   1 ( 1 )   1 - 13   2022.9

A Machine Learning Based Fuel Consumption Saving Method with Time and Environment Dependency Aware Management Reviewed

Peng Yu and Hiroyuki Yamauchi

5th International Conference on Electronics, Communications and Control Engineering (ICECC 2022)   MC1030   1 - 8   2022.3

Time and Environment Dependency Aware Fuel Consumption Tracking Method for Improving Drivers and Trucks Management Reviewed

Peng Yu, Jiazheng Xi and Hiroyuki Yamauchi

The 36th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2021)   CP-1 Computers   1 - 4   2021.6

A layer-wise ensemble technique for binary neural network Reviewed

Jiazhen Xi and Hiroyuki Yamauchi

International Journal of Pattern Recognition and Artificial Intelligence   35 ( 8 )   1 - 21   2021.6

A Dual-Split 6T SRAM based Computing-in-Memory Unit-Macro with Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors Reviewed

Xin Si;Win-San Khwa;Jia-Jing Chen;Jia-Fang Li;Xiaoyu Sun;Rui Liu;Shimeng Yu;Hiroyuki Yamauchi; Qiang Li ;Meng-Fan Chang

IEEE Transactions on Circuits and Systems I: Regular Papers   66 ( 11 )   4171 - 4185   2019.11

A 28nm 320Kb TCAM Macro using Split-Controlled Single-Load 14T Cell and Triple Margin Voltage Sense Amplifier Reviewed

Cheng-Xin Xue, Wei-Cheng Zhao,Tzu-Hsien Yang, Yi-Ju Chen, Hiroyuki Yamauchi,Meng-Fan Chang

IEEE Journal of Solid-State Circuits   54 ( 10 )   2743 - 2753   2019.10

A Deconvolution Error Avoidance Technique for Iterative Expectation–Maximization Algorithm Reviewed

Hiroyuki Yamauchi

International Conference on Computer Science and Engineering (ICCSE2019)   2019.2

A 28nm 320Kb TCAM Macro with Sub-0.8ns Search Time and 3.5+x Improvement in Delay-Area-Energy Product using Split-Controlled Single-Load 14T Cell Reviewed

Cheng-Xin Xue, Wei-Cheng Zhao, Tzu-Hsien Yang, Yi-Ju Chen, Hiroyuki Yamauchi and Meng-Fan Chang

IEEE Asia Solid-State Circuits Conference (A-SSCC),   pp. 127-128   2018.11

A Dual-Split-Controlled 4P2N 6T SRAM in Monolithic 3D-ICs with Enhanced Read Speed and Cell Stability for IoT Applications Reviewed

Wei-Hao Chen , Chien-Fu Chen, Yi-Ju Chen, Hsiao-Yun Chiu, Chang-Hong Shen, Jia-Min Shieh , Fu-Kuo Hsueh, Chih-Chao Yang, Bo-Yuan Chen, Guo-Wei Huang, Kai-Shin Li, Wen-Kuan Yeh, Hiroyuki Yamauchi, and Meng-Fan Chang

IEEE Electron Device Letters (EDL)   Vol.39 ( No.8 )   pp.1167-1170   2018.8

A Segmentation Kernel Fitting Technique to Circumvent Extreme Deviation from Exponentially Descent Tail Distribution Reviewed

Worawit Somha, Hiroyuki Yamauchi,

International Journal of Electrical and Electronic Engineering & Telecommunications (IJEEET)   Vol.7 ( No.3 )   pp.114-118   2018.7

An Error Reduction Technique in Richardson-Lucy Deconvolution Method Reviewed

Hiroyuki Yamauchi, Worawit Somha

IOP Conf. Series: Journal of Physics: Conf. Series 1047 (2018) 012017   1047   1 - 13   2018.7

A Column Reduction Technique for In-memory Machine Learning Classifier Reviewed

Jiazhen Xi and Hiroyuki Yamauchi

International Journal of Machine Learning and Computing (IJMLC)   Vol.8 ( No.2 )   127 - 132   2018.4

A Column Reduction Technique for In-memory Machine Learning Classifier Reviewed

Jiazhen Xi, and Hiroyuki Yamauchi

9th International Conference on Signal Processing Systems (ICSPS 2017)   2017.11

A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme Reviewed

Meng-Fan Chang; Chien-Fu Chen; Ting-Hao Chang; Chi-Chang Shuai; Yen-Yao Wang; Yi-Ju Chen; Hiroyuki Yamauchi

IEEE Journal of Solid-State Circuits   52 ( 9 )   Pages: 2498 - 2514   2017.9

A Time-dependent Variability Impact Reduction Technique for Down-Sampling Images In-memory Machine Learning Classifier Reviewed

Jiazhen Xi, and Hiroyuki Yamauchi

The 32nd International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2017)   pp.1-4   2017.7

A Deconvolution Error Avoidance Technique in Richardson-Lucy Method Reviewed

Hiroyuki Yamauchi, Worawit Somha

9th International Conference on Inverse Problems in Engineering (ICIPE2017)   pp.1-12   2017.5

A mutual rectification-interference avoidance technique with cascade filters for both downward- direction tailed-RDF deconvolution Reviewed

Hiroyuki Yamauchi, Worawit Somha

IEEE　29th Symposium on Integrated Circuits and Systems Design (SBCCI)   DOI 10.1109/SBCCI.2016.7724039   1 - 6   2016.9

A parallel filter technique to stabilize error-rectification behavior in RDF deconvolution process for SRAM screening test Reviewed

Hiroyuki Yamauchi, Worawit Somha

IEEE technical-co-sponsored SAI Computing Conference   DOI:10.1109/SAI.2016.7556092   1 - 6   2016.8

A Filter Design for Reverse Engineering with Blind Deconvolution to Retrieve Unknown?RDF/RTN Factors from SRAM Margin Variations Reviewed

Hiroyuki Yamauchi, Worawit Somha

Inverse Problems Symposium 2016   1 - 6   2016.5

A filter design for blind deconvolution to decouple unknown RDF/RTN factors from complexly coupled SRAM margin variations Reviewed

Hiroyuki Yamauchi, Worawit Somha

IEEE 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)   DOI: 10.1109/LASCAS.2016.7451056   247 - 250   2016.4

A Noise Suppressing Filter Design for Reducing Deconvolution Error of Both-Directions Downward Sloped Asymmeric RTN Long-Tail Distributions Reviewed

Hiroyuki Yamauchi, Worawit Somha

IEEE 6th International Workshop on CMOS Variability (VARI) 2015   DOI: 10.1109/VARI.2015.7456563   51 - 56   2015.9

A Phase Shifting Multiple Filter Design Methodology for Lucy-Richardson Deconvolution of Log-Mixtures Complex RTN Tail Distribution Reviewed

Hiroyuki Yamauchi, Worawit Somha

IEEE 28th Symposium on Integrated Circuits and Systems Design SBCCI2015   DOI: http://dx.doi.org/10.1145/2800986.2800996   2015.8

Feedback Gain Phase Alignment Effects on Convergence Characteristics in Lucy-Richardson Deconvolution for Inversely Predicting Complex-Shaped RTN Distributions Reviewed

Hiroyuki Yamauchi, Worawit Somha

IEEE 58th International Midwest Symposium on Circuits and Systems   DOI: 10.1109 MWSCAS.2015.7282140   572 - 575   2015.8

A Filter Design to Increase Accuracy of Lucy- Richardson Deconvolution for Analyzing RTN Mixtures Effects on VLSI Reliability Margin Reviewed

Hiroyuki Yamauchi, Worawit Somha,Mr. Yuan-Qiang Song

IEEE 28th IEEE International System-on-Chip Conference (SOC)   DOI: 10.1109 SOCC.2015.7406925   121 - 126   2015.8

Ringing Error Prevention Techniques in Lucy-Richardson Deconvolution Process for SRAM Space-Time Margin Variation Effect Screening Designs Reviewed

Hiroyuki Yamauchi, Worawit Somha

IEEE The Latin-American Test Symposium (LATS)   DOI: 10.1109/LATW.2015.7102402   2015.3

A 28nm 256kb 6T-SRAM with 280mV Improvement in VMIN Using a Dual-Split-Control Assist Scheme Reviewed

M-F. Chang, C-F. Chen, T-H. Chang, C-C. Shuai ,Y-Y. Wang,H. Yamauchi

2015 IEEE International Solid-State Circuits of Conference   DOI: 10.1109/ISSCC.2015.7063052   314 - 315   2015.2

A Practical Solution to Ringing Error Problems with Lucy-Richardson Deconvolution for Spatiotemporal SRAM Margin Variation Effect Analyses Reviewed

Hiroyuki Yamauchi and Worawit Somha

ICEIC (International Conference on Electronics, Information and Communication) 2015   378 - 381   2015.1

Deconvolution Algorithm Dependencies of Estimation Errors of RTN Effects on Subnano-Scaled SRAM Margin Variation Reviewed

Hiroyuki Yamauchi, Worawit Somha

IEEE VLSI-SOC 2014   DOI: 10.1109/VLSI-SoC.2014.7004191   pp 97-102   2014.10

Errors in Solving Inverse Problem for Reversing RTN Effects on VCCmin Shift in SRAM Reliability Screening Test Designs Reviewed

Hiroyuki Yamauchi, Worawit Somha

IEEE SOC 2014   DOI: 10.1109/SOCC.2014.6948947   pp 318-323   2014.9

Comparative Study on Deconvolution Function Dependencies of RTN/RDF Effect Estimation Errors in Analyzing Sub-nm-Scaled SRAM Margins Reviewed

Hiroyuki Yamauchi, Worawit Somha

IEEE MWSCAS 2014   DOI: 10.1109/MWSCAS.2014.6908394   230 - 233   2014.8

An Adaptively Segmented Forward Problem Based Non-Blind Deconvolution Technique for Analyzing SRAM Margin Variation Effects Reviewed

Worawit Somha, Hiroyuki Yamauchi

Journal of Semiconductor Technology and Science   Vol.14 ( No.4 )   365 - 375   2014.8

A Comparative Study on RTN Deconvolution of Richardson-Lucy and Proposed Partitioned Means for Analyzing SRAM Fail-Bit Prediction Accuracy　 Reviewed

Worawit Somha, Hiroyuki Yamauchi

International Journal of Computer and Comminication Engineering   Vol. 3 ( No. 3 )   178 - 183   2014.5

A Comparative Study on RTN Deconvolution of Richardson-Lucy and Proposed Partitioned Means for Analyzing SRAM Fail-Bit Prediction Accuracy Reviewed

Worawit Somha, Hiroyuki Yamauchi

2014 3rd International Conference on Network and Computer Science   vol.3 ( no.3 )   178 - 183   2014.3

A technique to solve issue of Richardson-Lucy deconvolution for analyzing RTN effects on SRAM margin variation Reviewed

Hiroyuki Yamauchi, Worawit Somha

IEEE Circuits and Systems (LASCAS), 2014 IEEE 5th Latin American Symposium on   DOI: 10.1109/LASCAS.2014.6820250   1 - 4   2014.2

A Comparative Review of Application Dependencies of Deconvolution Errors between Algebraic and Nonlinear Optimization in SRAM Margin Analyses Reviewed

Worawit Somha, Hiroyuki Yamauchi

2014　International Conference on Electronics, Information and Communication (ICEIC)   154 - 155   2014.1

An RTN Variation Tolerant SRAM Screening Test Design with Gaussian Mixtures Approximations of Long-Tail Distributions Reviewed

Worawit Somha, Hiroyuki Yamauchi

Journal of Electronic Testing Theory and Applications   Vol. 30, No.2 ( ISSN 0923-8174 )   171 - 181   2014.1

A Technique to Circumvent V-shaped Deconvolution Error for Time-dependent SRAM Margin Analyses Reviewed

Worawit Somha, Hiroyuki Yamauchi, Ma Yuyu

IEIE Transactions on Smart Processing and Computing, vol. 2, no. 4, August 2013   Vol.2 ( No.4 )   216 - 225   2013.12

Iterative and Adaptively Segmented Forward Problem Based Non-Blind Reviewed

Worawit Sohma, Hiroyuki Yamauchi, Ma Yuyu

International System On Chip Conference (ISOCC) 2013   TBD   2013.11

Iterative and Adaptively Segmented Forward Problem Based Non-Blind Deconvolution Technique for Analyzing SRAM Margin Variation Effects Reviewed

Worawit Somha, Hiroyuki Yamauchi, Ma Yuyu

International System On Chip Conference (ISOCC) 2013   pp184-187   2013.11

Blind Deconvolution Technique for Extracting Unknown Two Factors of RTN and Truncated RDF from Given Target for Overall SRAM Margin Variations Reviewed

Worawit Somha, Hiroyuki Yamauchi, Ma Yuyu

International System On Chip Conference (ISOCC) 2013   PP188-191   2013.11

Adaptive Segmentation Gaussian Mixtures Models for Approximating to Drastically Scaled-Various Sloped Long-Tail RTN Distributions Reviewed

Worawit Somha and Hiroyuki Yamauchi

International　Journal of Future Computer and Communication   Vol.2 ( No.5 )   407 - 412   2013.10

A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V$_{rm TH}$ Read-Port, and Offset Cell VDD Biasing Techniques Reviewed

Chen, M.-P. ; Chen, L.-F. ; Yang, S.-M. ; Kuo, Y.-J. ; Wu, J.-J. ; Su, H.-Y. ; Chu, Y.-H. ; Wu, W.-C. ; Yang, T.-Y. ; Yamauchi, H.

Solid-State Circuits, IEEE Journal of (Volume:48 , Issue: 10 )   Volume:48 ( Issue: 10 , 10.1109/JSSC.2013.2273835 )   2558 - 2569   2013.10

A Discussion on SRAM Forward/Inverse Problem Analyses for RTN Long-Tail Distributions Reviewed

Worawit Somha, Hiroyuki Yamauchi, Ma Yuyu

IEEE Computer society International Symposium on VLSI (ISVLSI)   DOI: 10.1109/ISVLSI.2013.6654623   2013.8

A Discussion on RTN Variation Tolerant Guard Band Design Based on Approximation Models of Long-Tail Distributions for Nano-Scaled SRAM Screening Test Reviewed

Worawit Somha and Hiroyuki Yamauchi

International　Journal of Computer and Electrical Engineering   Vol.5 ( No.4, )   366 - 371   2013.8

A Technique to Circumvent Problematic Deconvolution Processes in Time-dependent SRAM Margin Analyses Reviewed

Worawit Somha, Hiroyuki Yamauchi, Ma Yuyu

International Conference on Engineering,Applied Sciences, and Technology   IS-6 ( ICT-Application 6 )   ID024 pp11-16   2013.8

A Comparative Review of Deconvolution Errors in SRAM Margin Analyses between Algebraic and Optimization Problem Based Approaches Reviewed

Worawit Somha, Hiroyuki Yamauchi, Ma Yuyu

International Conference on Engineering,Applied Sciences, and Technology   IS-6 ( ICT-Application 6 )   ID050 pp.60-65   2013.8

'A Discussion on Random Telegraph Noise (RTN) Effects on SRAM Array VCCmin Modulation and Its Dependencies of VCC and RTN Distribution' Reviewed

Ma Yuyu, Hiroyuki Yamauchi, Worawit Sohma

ITC-CSCC2013   294 - 296   2013.7

A 210mV 7.3MHz 8T SRAM with Dual Data-Aware Write-Assists and Negative Read Wordline for High Cell-Stability, Speed and Area-Efficiency Reviewed

C. F. Chen, T.-H. Chang, L.-F. Chen, M.-F. Chang, and H. Yamauchi

IEEE 2013 Symposium on VLSI Circuits Dig. Tech. Papers   2013   130 - 131   2013.6

A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms Reviewed

Meng-Fan Chang ,Chih-Sheng Lin ; Wei-Cheng Wu ; Ming-Pin Chen ; Yen-Huei Chen ; Zhe-Hui Lin ; Shyh-Shyuan Sheu ; Tzu-Kun Ku ; Cha-Hsin Lin ; Yamauchi, H.

IEEE Journal of Solid-State Circuits   Volume:48 ( Issue:6 )   pp.1521-1529   2013.6

A Look up Table Based Adaptive Segmentation Gaussian Mixtures Model for Fitting Complex Long-Tail RTN Distributions Reviewed

Worawit Somha and Hiroyuki Yamauchi

International　Journal of Materials, Mechanics and Manufacturing   Vol.1 ( No.3 )   245 - 250   2013.6

A Nano-Scaled SRAM Guard Band design with Gaussian Mixtures Model of Complex Long Tail RTN Distributions Reviewed

Worawit Somha, Hiroyuki Yamauchi

World Academy of Science, Engineering and Technology   Vo. 75   PP.704-714   2013.6

RTN Variation Tolerant Screening Test Using Accelerated Margin Shifts for Nano-Scaled SRAM Reviewed

Worawit Somha, Hiroyuki Yamauchi (Fukuoka Institute of Technology, JP)

18th IEEE European Test Symposium, May 27-31, 2013   P3.3 Workshop-type/Work-in-Progress ( POSTER SESSION P3 )   2013.5

Convolution/Deconvolution SRAM Analyses for Complex Gamma Mixtures RTN Distributions Reviewed

Worawit SOMHA, Hiroyuki YAMAUCHI

International Conference on IC Design and Technology   2013.5

Adaptive Segmentation Gaussian Mixtures Models for Approximating to Drastically Scaled-Various Sloped Long-Tail RTN Distributions Reviewed

Worawit Somha and Hiroyuki Yamauchi

2013 2nd International Conference on Network and Computer Science (ICNCS 2013)   Vol.2 ( No.5 )   407 - 412   2013.4

Convolution/deconvolution SRAM analyses for complex gamma mixtures RTN distributions Reviewed

Worawit Somha and Hiroyuki Yamauchi

2013 International Conference on Electronics Engineering and Technology   Vol.5 ( No.4 )   366 - 371   2013.4

A Look up Table Based Adaptive Segmentation Gaussian Mixtures Model for Fitting Complex Long-Tail RTN Distributions Reviewed

Worawit Somha and Hiroyuki Yamauchi

2013 International Conference on Nano and Materials Engineering   Vol.1 ( No.3 )   245 - 250   2013.4

An RTN Variation Tolerant Guard Band Design for a Deeper Nanometer Scaled SRAM Screening Test: Based on EM Gaussians Mixtures Approximations Model of Long-Tail Distributions Reviewed

Worawit SOMHA, Hiroyuki YAMAUCHI

14th IEEE Latin-American Test Workshop   Session 9-1   DOI:10.1109/LATW.2013.6562687   2013.4

A Nano-Scaled SRAM Guard Band Design with Gaussian Mixtures Model of Complex Long Tail RTN Distributions Reviewed

Worawit Somha, Hiroyuki Yamauchi

2013 International Journal of Electrical and Electronics Engineering   Session-I   2013.3

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory Reviewed

Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Ya-Chin King, Chorng-Jung Lin, Hung-Jen Liao, Yu-Der Chih, and Hiroyuki Yamauchi

IEEE Journal of Solid-State Circuits 　   Vol.48 ( No.3 )   864 - 877   2013.3

Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement Reviewed

Shu-Meng Yang, Meng-Fan Chang, Chi-Chuang Chiang, Ming-Pin Chen, and Hiroyuki Yamauchi

IEEE Journal of Solid-State Circuits   Vol.48 ( N0.2 )   pp613-623   2013.2

Fitting Mixtures of Gaussians to Heavy-Tail Distributions to Analyze Reviewed

Worawit Somha, Hiroyuki Yamauchi, Yan Zhang

(Advanced Materials Research 2013) Trans Tech Publications   Vol. 677   317 - 325   2013.2

Fitting Mixtures of Gaussians to Heavy-Tail Distributions to Analyze Reviewed

Worawit Somha, Hiroyuki Yamauchi, Yan Zhang

2013 2nd International Conference on Micro Nano Devices, Structure and Computing Systems(MNDSCS 2013)   Vol. 677   317 - 325   2013.1

A 260mV L-shaped 7T SRAM with Bit-Line (BL) Swing Expansion Schemes Based on Boosted BL, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques Reviewed

H.Yamauchi, M.F.Chen, et al

IEEE Symposium on VLSI Circuits   2012.6

Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in A 40nm Fully Functional Embedded SRAM Reviewed

Yen-Huei Chen, Shao-Yu Chou, Quincy Lee2, Wei-Min Chan2, Dar Sun2, Hung-Jen Liao2, Ping Wang2, Meng-Fan Chang, Hiroyuki Yamauchi

IEEE Journal of Solid-State Circuits 　   Volume: 47 ( Issue: 4 )   969 - 980   2012.4

Endurance-Aware Circuit Designs of Nonvolatile Logic and Nonvolatile SRAM Using Resistive Memory (Memristor) Device Reviewed

Meng-Fan Chang, Ching-Hao Chuang, Min-Ping Chen, Lai-Fu Chen (National Tsing Hua Univ., Taiwan), Hiroyuki Yamauchi (Fukuoka Inst. of Tech., Japan), Pi-Feng Chiu, Shyh-Shyuan Sheu (Electronics and Optoelectronics Research Laboratories, Industrial Technology Research Institute (ITRI), Japan)

The 17th Asia and South Pacific Design Automation Conference   pp. 329 - 334   2012.2

A 40nm Fully Functional SRAM with BL Swing and WL Pulse Measurement Scheme for Eliminating a Need for Additional Sensing Tolerance Margins Reviewed

Y.-H. Chen*,**, S.- Y. Chou*, Q. Lee*, W.-M. Chan*, D. Sun*, H.-J. Liao*, P. Wang*, M.-F. Chang** and H. Yamauchi***

IEEE Sympsoium on VLSI Circuits   Session 7-1   2011.6

A Larger Stacked Layer Number Scalable TSV-Based 3D-SRAM for High-Performance Universal-Memory-Capacity 3D-IC Platforms Reviewed

M.-F. Chang*, W.-C. Wu*, C.-S. Lin**, P.-F. Chiu**, M.-B. Chen*,**, Y.-H. Chen*,***, H.-C. Lai**, Z.-H. Lin**, S.-S. Sheu**, T.-K. Ku** and H. Yamauchi****

IEEE Symposium on VLSI Circuits   Session 7-3   2011.6

A Large σVTH/VDD Tolerant Zigzag 8T SRAM with Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme Reviewed

Jui-Jen Wu, Yen-Huei Chen, Meng-Fan Chang, Po-Wei Chou, Chien-Yuan Chen, Hung-Jen Liao, Ming-Bin Chen, Yuan-Hua Chu, Wen-Chin Wu, and Hiroyuki Yamauchi

IEEE Journal of Solid-State Circuits   Vol.46 ( No.4 April )   815 - 827   2011.4

An Offset-Tolerant Current-Sampling-Based Sense Amplifier for Sub-100nA-Cell-Current Nonvolatile Memory Reviewed

M-F.Chang, Hiroyuki Yamauchi

IEEE International Solid State Circuits Conference   ISSCC2011   2011.2

A Large σVth/VDD Tolerant Zigzag 8T SRAM with Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme Reviewed

JJ Wu, YH-Chem, MG Chang, Hiroyuki Yamauchi, et al,..

IEEE Symposium on VLSI Circuits 2010   Session 4   2010.6

A Low Vth SRAM Reducing Mismatch of Cell-Stability with An Elevated Cell Biasing Scheme Reviewed

Hiroyuki Yamauchi

IEEK JOURNAL OF SEMICONDUCTOR TECHNOLOY AND SCIENCE   Vol10 ( N0.2 )   PP.118-129   2010.6

A Differential Data Aware Power-supplied (D2AP) 8T SRAM cell with Expanded Write/Read Stabilities for Lower VDDmin Applications Reviewed

Meng-Fan Chang, Jui-Jen Wu, Kuang-Ting Chen, Yung-Chi Chen, Yen-Hui Chen, Robin Lee, Hung-Jen Liao, and Hiroyuki Yamauchi

IEEE Journal of Solid-State Circuits   Vol.45 ( No.6 )   1234 - 1245   2010.6

A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies　 Reviewed

Hiroyuki Yamauchi

IEEE Transactions on Very Large Scale Integration (VLSI) Systems   18 ( 5 )   763 - 774   2010.5

A 0.29V Embedded NAND-ROM in 90nm CMOS for Ultra Low Voltage Applications Reviewed

C.M.-Fan, H.Yamauchi

2010 IEEE International Solid-State Circuits of Conference   2010.2

Prospects for Variation Tolerant SRAM Circuit Designs Reviewed

Hiroyuki Yamauchi

IEEE ASICON 2009   2009.10

Variation Tolerant SRAM Circuit Design Trend in a Deeper Nanometer-Scale Technology Reviewed

Hirfoyuki Yamauchi

IEEE MTDT 2009   2009.8

A Differential Data Aware Power-Supplied (D2AP) 8T SRAM Cell with Expanded Write/Read Stabilities for Lower VDDmin Applications Reviewed

Hiroyuki Yamauchi

IEEE Symposium on VLSI Circuits 2009, has presented at Kyoto June, 2009   2009.6

A 0.6V Dual-rail Compiler SRAM Design on 45nm CMOS Technology with Adaptive SRAM Power for Lower VDD_min VLSIs Reviewed

Yen Huei Chen, Gary Chan, Shao Yu Chou, Hsien-Yu Pan, Jui-Jen Wu, Robin Lee, H. J. Liao (TSMC), and　Hiroyuki Yamauchi(福岡工業大学)

IEEE IEEE Journal of Solid State Circuits   Vol. 44 ( No. 4 )   pp. 1209-1215   2009.4

A Scaling Trend of Variation-Tolerant SRAM Circuit Design in Deeper Nanometer Era Reviewed

Hiroyuki Yamauchi

IEEK JOURNAL OF SEMICONDUCTOR TECHNOLOY AND SCIENCE   VOL.9, NO.1, MARCH, 2009 ( VOL.9, NO.1 )   pp.37-50   2009.3

Variation Tolerant SRAM Designs Reviewed

Hiroyuki Yamauchi

IEEE International Solid-State-Circuit-Confernce (ISSCC) 2009 Tutorial   2009.2

A Discussion on SRAM Circuit Design Trend in Deeper Nano-meter Era Reviewed

H.Yamauchi

International SOC design conf. ISOCC2008   2008.10

An Over-1Gb/s Transceiver Core to Large SoCs for Consumer Electronics Reviewed

Takefumi Yoshikawa, Takashi Hirata, Tsuyoshi Ebuchi, Toru Iwata, Yukio Arima , Hiroyuki Yamauchi

IEEE Transactions on Very Large ScaleIntegration Systems   Vol.16 ( No.9 )   pp. 1187-1198   2008.9

A Stable 2-Port SRAM Cell Design Against　Simultaneously Read/Write-Disturbed Accesses　 Reviewed

Hiroyuki Yamauchi Toshikazu Suzuki(Panasonic), Hiroyuki Yamauchi(福岡工業大学), Yoshinobu Yamagami, Katsuji Satomi, and Hironori Akamatsu

IEEE Journal of Solid State Circuits   Vol. 43 ( No. 9 )   pp. 2109-2119   2008.9

A 0.6V 45nm Adaptive Dual-rail SRAM Compiler Circuit Design for Lower VDD_min VLSIs Reviewed

Hiroyuki Yamauchi

IEEE Symposium on VLSI Circuits 2008   2008.6

An embedded SRAM and its Scaling trend Reviewed

山内 寛行

IEEE International Solid-State-Circuit-Conference (ISSCC) 2009 Tutorial ISSCC2008, Advanced Circuit Memory Forum “Embedded memory”   2008.2

Embedded SRAM Trend in Nano-Scale CMOS Reviewed

山内 寛行

IEEE MTDT 2007   2007.12

A Review and Perspect for Embedded SRAM Circuit Design for 45nm and beyond Reviewed

山内 寛行

2007 IEEE The 7Th International Conference   2007.10

A 45nm Dual-Port SRAM with Write and Read Capability Enhancement at Low Voltage Reviewed

山内 寛行

2007 IEEE International System on Chip Conference   2007.9

A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme Reviewed

山内 寛行

2007 IEEE Custom Integrated Circuits Conference   2007.9

Embedded SRAM Circuit Design Technologies for a 45nm and beyond Reviewed

H.Yamauchi

IEEE ASICON 2007   2007.8

A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-volatile Memory Cell Design with a Differential Cell Architecture in a 110nm Pure CMOS Logic Process for a System LSI IEICE Transactions on Electronics Reviewed

Yasue Yamamoto , Masanori Shirahama, Toshiaki Kawasaki, Ryuji Nishihara, Shinichi Sumi, Yasuhiro Agata, Hirohito Kikukawa,Hiroyuki Yamauchi,(福岡工業大学)

」IEICE Transactions on Electronics.   Vol.E90-C ( No.5 )   1129 - 1137   2007.5

A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving Against Simultaneous Read/Write Disturbed Accesses Reviewed

Hiroyuki Yamauchi（福岡工業大学),　 Toshikazu Suzuki, Yoshinobu Yamagami（Panasonic)

IEICE Transactions on Electronics.   Vol.E90-C ( No.4 )   pp.749-757   2007.4

An Embedded SRAM design Reviewed

山内 寛行

2006 IEEE Asian Solid State Circuits Conference   2006.11

A Differential Cell Terminal Biasing Scheme Enabling A Stable Write Operation Against A Large Random Threshold Voltage (Vth) Variation Reviewed

Hiroyuki Yamauchi（福岡工業大学),　 Toshikazu Suzuki, Yoshinobu Yamagami（Panasonic)

IEICE Transactions on Electronics.   Vol.E89-C ( No.11 )   pp.1526-1534   2006.11

Ａ Sub-0.5V Operating Embedded SRAM Featuring a Multi-Bit-Error-Immune Hidden-ECC Scheme Reviewed

T.Suzuki, Y.Yamagami, I..Hatanaka, A.Shibayama, H.Akamatsu

IEEE Journal of Solid –State Circuits   Vol.41 ( No.1 )   152 - 160   2006.1

A Stable SRAM Cell Design Against A Simultaneously R/W Disturbed Accesses Reviewed

山内 寛行

IEEE Symposium on VLSI Circuits Digest of Technical Papers   2 ( 2 )   14 - 15   2006

「A 322MHz Random-Cycle Embedded DRAM with High-Accuracy Sensing and Tuning Reviewed

M.Iida, N.Kuroda, H.Otsuka, M.Hirose, Y.Yamasaki, K.Ota, K.Shimakawa, T.Nakabayashi (Panasonic), Hiroyuki Yamauchi

」IEEE Journal of Solid –State Circuits   Vol.40 ( No.11 )   2296 - 2304   2005.11

A 400MHz Random Cycle Dual-port interleaved DRAM(D2RAM) with Standard CMOS Process Reviewed

M.Shirahama, Y.Agata, T.Kawasaki, R.Nishihara, W.Abe, N.Kuroda, H.Sadakata, K.Takahashi, K.Egashira, H.Honda, M.Miura, S.Hashimoto, H.Kikukawa,

IEEE Journal of Solid –State Circuits   Vol.40 ( No.05 )   1200 - 1207   2005.5

0.3-0.5V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier Reviewed

T.Suzuki, Y.Yamagami, I.Hatanaka, A.Shibayama, H.Akamatsu,

IEICE Transactions on Electronics.   Vol.E88-C ( No.4 )   630 - 638   2005.4

A 400MHz Random Cycle Dual-port interleaved DRAM with Reviewed

M.Shirahama,Y.Agata, H.Yamauchi

ISSCC 2005, Technical Digest Papers   2005.2

0.3-1.5V Embedded SRAM with Device-　Fluctuation-Tolerant Access Control and Cosmic-Ray-Immune Hidden-ECC Scheme Reviewed

T.Suzuki, H.Yamauchi

Technical Digest Papers　of IEEE　ISSCC 2005   2005.2

0.3-1.5V Embedded SRAM with Device-Fluctuation Tolerant Access-Control and Cosmic-Ray-Immune Hidden-ECC Scheme Reviewed

山内 寛行

IEEE Technical Digest Papers of ISSCC2005   484 - 485   2005.2

A 400MHz Random Cycle Dual-port interleaved DRAM with Striped-Trench Capacitor Reviewed

山内 寛行

IEEE Technical Digest Papers of ISSCC2005   462 - 463   2005.2

A 322MHz Random-Cycle Embedded DRAM with High-Accuracy Sensing and Tuning Reviewed

山内 寛行

IEEE Technical Digest Papers of ISSCC2005   460 - 461   2005.2

A 322MHz Random-Cycle Embedded DRAM with High-Accuracy Sensing and Tuning Reviewed

M.Iida, N.Kuroda, H.Yamauchi

IEEE ISSCC 2005, Technical Digest Papers   2005.2

A Rewritable CMOS-FUSE for System-on-Chip with a Differential Cell Architecture in a 0.13um CMOS Logic Process Reviewed

Hiroyuki Yamauchi, Yasunori Agata, Masanori Shirahama, Hirohito Kikukawa

IEICE Transactions on Electronics.   Vol.E87-C ( No.10 )   1664 - 1672   2004.10

An 800Mb/s Physical Layer LSI with Hybrid Port Architecture for Consumer Electronics Networking Reviewed

T. Yoshikawa, T. Yoshida,,, H.Yamauchi

2002 Technical Digest of IEEE International Solid-State Circuits Conference   2002.2

A 1.25Gb/s CMOS receiver core with Plesiochronous clocking capability for asynchronous burst data acquisition Reviewed

Takefumi Yoshikawa,Tadahiro Yoshida,Tsuyoshi Ebuchi,Hiroyuki Yamauchi

2000 IEEE International Solid-State Circuits Conference   2000.2

A 0.5V Single Power Supply Operated High-Speed Boosted and Offset-Grounded Data Storage (BOGS) SRAM Cell Architecture Reviewed

Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, and Akira Matsuzawa,

IEEE Transactions on Very Large Scale Integration (VLSI) Systems   Vol.5 ( No.4 )   pp. 377-387   1997.12

A Low Power Data Storage Circuit with an Intermittent Power Supply Scheme for Sub-1V MT-CMOS Reviewed

HIronori Akamatsu, Tohru Iwata, Hiroyuki Yamauchi, HIsakazu Kotani, Hiro Yamamoto, Takashi Hirata

IEICE Transaction on Electronics,Vol.E80-C,No.12, December,1997,   Vol.E80-C ( No.12 )   pp. 1572-1577   1997.12

Studies on low power technologies for battery-operated semiconductor random access memories Invited Reviewed International coauthorship International journal

山内 寛行

1997.7

Gate Over-Driving CMOS Architecture for 0.5V Single Power-Supply Operated Devices Reviewed

Toru Iwata, Hiroyuki Yamauchi

1997　IEEE International Solid-State Circuits Conference   1997.2

Plate Bumping Memory-cell Leakage Current Measurement method and its Application to Data Retention Characteristic Analysis for RJB DRAM Reviewed

Tohru Iwata, Hiroyuki Yamauchi

IEICE Transaction on Electronics   Vol.E79-C ( No.12 )   pp.1707-1712   1996.12

A Signal-Swing Suppressing Strategy for Power and Layout Area Saving Using Time-　Multiplexed Differential Data　Transfer Scheme Reviewed

Hiroyuki Yamauchi ,Akira Matsuzawa

IEEE Journal of Solid-State Circuits   Vol.31 ( No.9 )   pp. 1285-1294   1996.9

A 0.5V/100MHz Over Vcc Grounded Data Storage (OVGS) SRAM Cell Architecture with Boosted Bit-line and Offset Source Over-Driving Schemes Reviewed

Hiroyuki Yamauchi ,Toru Iwata,Hironori Akamatsu,Akira Matsuzawa

1996 International Symposium on Low Power Electronics and Design   1996.8

A 0.8V/100MHz/sub-5mW-Operated Mega-bit SRAM Cell Architecture with Charge-Recycle Offset-Source Driving (OSD) Scheme Reviewed

Hiroyuki Yamauchi ,Toru Iwata,Hironori Akamatsu,Akira Matsuzawa

1996 IEEE Symposium on VLSI Circuits   1996.6

A Low Power Data Holding Circuit with an Intermittent Power Supply Scheme for sub-1V MT-CMOS LSIs Reviewed

Hironori Akamatsu,Toru Iwata, Takashi Hirata,Hiroyuki YamauchiHisakazu Kotani,Hiro Yamamoto, Akira Matsuzawa

1996 IEEE Symposium on VLSI Circuits   1996.6

A Circuit Technology for Self-Refresh 16Mb DRAM with Less than 0.5μA/MB Reviewed

Hiroyuki Yamauchi,Toru Iwata, Akito Uno, Masanori Fukumoto, Tsutomu Fujita

IEEE Journal of Solid-State Circuits   Vol.30 ( No.11 )   No.11   1995.11

A Low Power Signal-Swing Suppressing Strategy Using Time-Multiplexed Differential Data-Transfer (TMD) Scheme Reviewed

Hiroyuki Yamauchi,Akira Matsuzawa

1995 IEEE Symposium on Low Power Electronics   1995.10

Charge-Recycling Bus Architecture for Battery-Operated Ultrahigh Data Rate ULSI’s Reviewed

Hiroyuki Yamauchi ,Hironori Akamatsu, Tsutomu Fujita (Panasonic)

IEICE Transaction on Electronics   Vol.E78-C ( No.6 )   pp. 671-679   1995.6

An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultrahigh Data Rate ULSI’s Reviewed

Hiroyuki Yamauchi ,Hironori Akamatsu, Tsutomu Fujita

IEEE Journal of Solid　-State Circuits   Vol.30 ( No.4 )   p. 423-431   1995.4

A Low Power Bus Architecture with Local and　Global Charge　-　Recycling Bus Techniques for Battery　-Operated Ultra-High Data Rate ULSI’s Reviewed

Hiroyuki Yamauchi ,Hironori Akamatsu, Tsutomu Fujita

IEICE Transaction on Electronics   Vol.E78-C ( No.4 )   pp. 394-403   1995.4

A Sub-0.5µA/MB Data-Retention DRAM Reviewed

Hiroyuki Yamauchi ,Toru Iwata, Akito Uno, Masanori Fukumoto, Tetusyuki Fukushima,Tsutomu Fujita

1995　IEEE International Solid-State Circuits Conference   1995.2

High-Speed Circuit Technologies for Battery-Operated 16Mbit CMOS DRAM Reviewed

Toshiaki Suzuki, Toru Iwata, Hironori Akamatsu, Akihiro Sawada, Toshiaki Tsuji, Hiroyuki Yamauchi, Takashi Taniguchi,Tsutomu Fujita

IEICE Transaction on Electronics   Vol.E77-C ( No.8 )   p. 1334-1342   1994.8

A Low Power Complete Charge-Recycling Bus Architecture for Ultra-High Data Rate ULSI's Reviewed

Hiroyuki Yamauchi ,Hironori Akamatsu, Tsutomu Fujita

1994 IEEE 1994 Symposium on VLSI Circuits   1994.6

Study of Tape Materials and Mounting Conditions For LOC Package Reviewed

T.Ochi, H.Funakoshi, S.Takehashi, H.Hatada, H.Tani, Hiroyuki Yamauchi,I Okumura, H.Honma

1994 IEEE International Microelectronics Conference   1994.4

A　Circuit Technology for High-Speed Battery-Operated 16Mb CMOS DRAM’s Reviewed

Hiroyuki Yamauchi , Toshiaki Suzuki,Akihiro Sawada, Tohru Iwata, Toshiaki Tsuji, Masashi Agata, Takashi Taniguchi, Yoshinori Odake, Kazuyuki Sawada, Teruhito Ohnishi, Masanori Fukumoto, Tsutomu Fujita, Michihiro Inoue (Panasonic)

IEEE Journal of Solid-State Circuits   Vol.28 ( No.11 )   pp. 1084-1091   1993.11

A 20ns Battery-Operated 16Mb CMOS DRAM Reviewed

Hiroyuki Yamauchi ,Toshiaki Suzuki,Akihiro Sawada, Tohru Iwata, Toshiaki Tsuji, Masashi Agata, Takashi Taniguchi, Yoshinori Odake, Kazuyuki Sawada, Teruhito Ohnishi, Masanori Fukumoto, Tsutomu Fujita, Michihiro Inoue

1993　IEEE International Solid-State Circuits Conference   1993.2

A Circuit Design to Suppress Asymmetrical Characteristics in High-Density DRAM Sense Amplifiers Reviewed

Hiroyuki Yamauchi , Toshiki Yabu, Toshio Yamada, Michihiro Inoue

IEEE Journal of Solid-State Circuits   Vol.25 ( No.1 )   pp. 36-41   1990.1

2007半導体テクノロジー大全「第2 編 第4 章 メモリ設計技術」

山内 寛行

Electronic Journal   2004 

ナノメーター時代のSRAM のリード/ライト同時ディスターブ・アクセスに対して安定なSRAM セル設計手法 の研究

山内 寛行

福岡工業大学 情報科学研究所 所報   18 巻   5 - 10   2007.10

A Power Saving Techniques for Machine Learning Edge Computing: Toward to an Era of AI Everywhere International conference

Hiroyuki Yamauchi

The 2nd International Conference on Electronics, Communications and Control Engineering (ICECC2019) 

Approximately Quantizing Algorithm for In-memory Machine Learning Classifier

カテイ セキ・鶴　隆介・山内寛行

第17回情報科学技術フォーラム FIT2018 

SRAMアレイ機械学習器のコラムイ削減手法

鶴隆介 ，セキ カテイ ，山内寛行

2018 年度第26回電子情報通信学会九州支部学生会講演会・講演論文集 

Comparison of ONEvsONE & ONEvsREST Methods

Yunshang Xiao, Jiazhen Xi, Hiroyuki Yamauchi

2017年度電子情報通信学会九州支部学生会講演会・講演論文集 

提供資源コストとリスポンスタイムの統計的な最適化問題

阿部悠大・山内寛行（福工大）

電気関係学会九州支部連合大会 

超階調度画像データ用逆畳み込みアルゴリズムの精度比較

宋 源強 ・山内寛行

電気関係学会九州支部学生会講演会 

提供資源コストとリスポンスタイムの統計的予測調査

宋 源強 ・山内寛行

電気関係学会九州支部学生会講演会 

IPシステムを介した遠隔操作・完全自律制御の実現

高本和馬、山内寛行（福岡工大）

電気関係学会九州支部連合大会 

A Discussion on SRAM Array Level VCC and Its Distribution Dependency Analyses of Random Telegraph Noise Effects

Yuyu Ma・Hiroyuki Yamauchi・Worawit Somha

電気関係学会九州支部連合大会 

ガウス分布とガンマ分布の畳み込み計算の簡易化のためのＥＭアルゴリズムを用いたガンマ分布のガウス分布による近似方法の提案

○張　妍・Worawit Somha・Hiroyuki Yamauchi（福岡工大）

電気関係学会九州支部連合大会 

ガンマ分布とガウス分布の畳み込み計算方法の提案

張 妍、山内寛行

電子情報通信学会九州支部学生講演会 

鉄道における電力供給システムのスマート化

○江頭晃規・山内寛行（福岡工大）

電気関連九州連合大会 

ガウス分布とガンマ分布の畳み込み計算の簡易化のためのガンマ分布のガウス分布による近似方法の提案

○張　妍・Worawit Somha・Hiroyuki Yamauchi（福岡工大）

電気関係学会九州支部連合大会 

重点的サンプリングを用いたSRAM Read Marginの統計解析における特性分布の関数化

桑野翔伍 山内寛行

第64回電気関係学会九州支部連合大会プログラム 

ジェスチャー認識の高度化のためのセンサー分散処理システムの研究

河内 宏史 　山内寛行

第19回電子情報通信学会九州支部　学生会講演会 

センサーノード拡張容易化制御システムの開発

江頭 晃規 　山内寛行

第19回電子情報通信学会九州支部　学生会講演会 

優先順位を考慮した入力インターフェースアルゴリズムの開発と実装

中田 紀之 　山内寛行

第19回電子情報通信学会九州支部　学生会講演会 

重点的サンプリングを用いたSRAM Read Marginの統計解析手法

貞方健太・山内寛行（福岡工大）

平成２２年度(第６３回)電気関係学会九州支部連合大会 

並列処理による画像からの色検出回路

河内宏史・平城幸範・山内寛行（福岡工大）

平成２２年度(第６３回)電気関係学会九州支部連合大会 

Zig-zag 8T SRAMの読み出し特性の改善

西　雅弘・山内寛行（福岡工大）

平成２２年度(第６３回)電気関係学会九州支部連合大会 

重点的サンプリングを用いたSRAM Read_Marginの解析手法

貞方健太・山内寛行（福岡工大）

電気関係学会九州支部第62回連合大会 

ＳＲＡＭの閾値電圧ばらつきによる書き込みマージンへの影響に関する研究

貞方健太 (福岡工大　情報工)、山内寛行 (福岡工大　情報工)、山野辺泰治 (福岡工大　情報工)

電気関係学会九州支部連合大会講演論文集 

ＳＲＡＭ同相・差動ソース電位制御の書き込みマージンの比較検討

山野辺泰治 山内寛行

電子情報通信学会大会講演論文集 

ＤＣ解析とＴｒａｎｓｉｅｎｔ解析によるＳＲＡＭの動作Ｍａｒｇｉｎの比較検討

横尾章一郎

電気関係学会九州支部連合大会講演論文集 

リード/ライト同時ディスターブ・アクセスに対して安定なSRAMセル設計手法(VLSI回路,デバイス技術(高速,低電圧,低消費電力))

鈴木 利一 , 山内 寛行 , 山上 由展 , 里見 勝治 , 赤松 寛範

電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス 106(206), 137-141, 2006-08-10  

リード／ライト同時ディスターブ・アクセスに対して安定なSRAMセル設計手法

鈴木利一（松下電器）・山内寛行（福岡工大）・山上由展・里見勝治・赤松寛範（松下電器）

電子情報通信学会 研究会 

2pSRAM の動作マージン拡大に適した電源制御手法

山内 寛行

電子情報通信学会SDM/ICD 共催研究会 

［招待講演］デジタル家電向け混載メモリの現状と将来展望　～ SoCの構造改革に向けたチャレンジ ～

山内寛行

電子情報通信学会 研究会 ICD 

デジタル家電向け混載メモリの現状と将来展望 : SoCの構造改革に向けたチャレンジ(新メモリ技術, メモリ応用技術, 一般, ISSCC特集2 DRAM)

山内 寛行

電子情報通信学会技術研究報告. ICD, 集積回路 105(1), 29-34, 2005-04-07  

ディジタルコンシューマ時代に向けたメモリ技術

佐藤 克之 , 山内 寛行 , 沼田 健二 , 赤沢 隆 , 片山 泰尚

電子情報通信学会技術研究報告. ICD, 集積回路 105(1), 59, 2005-04-07  

デジタル家電向け混載メモリの現状と将来展望 : SoCの構造改革に向けたチャレンジ

山内 寛行

電子情報通信学会技術研究報告. ICD, 集積回路 105(1), 29-34, 2005-04-07  

デジタルコンシューマ時代に向けたメモリ技術

佐藤克之（エルピーダメモリ）・山内寛行（松下電器）・沼田健二（東芝）・赤沢　隆（ルネサステクノロジ）・片山泰尚（日本IBM）

電子情報通信学会 研究会 

ハイブリッドポートアーキテクチャを備えた民生ネットワーク向け800Mb/s対応物理層LSIの開発

江渕 剛志 , 吉河 武文 , 吉田 忠弘 , 有馬 幸生 , 岩田 徹 , 西村 佳壽子 , 木村 博 , 小松 義英 , 山内 寛行

電子情報通信学会技術研究報告. ICD, 集積回路 102(83), 1-6, 2002-05-17  

高速クロックリカバリ用ビット変換回路の開発

江渕 剛志 , 吉河 武文 , 吉田 忠弘 , 山内 寛行

電子情報通信学会総合大会講演論文集 2000年.エレクトロニクス(2), 155, 2000-03-07  

高速インターフェイス用低消費電力同相電位発生回路の提案

小松 義英 , 赤松 寛範 , 平田 貴士 , 寺田 裕 , 高橋 学志 , 山内 寛行

電子情報通信学会総合大会講演論文集 2000年.エレクトロニクス(2), 160, 2000-03-07  

低電圧動作高速シリアルインタフェース用ドライバ回路

平田 貴士 , 赤松 寛範 , 高橋 学志 , 寺田 裕 , 小松 義英 , 山内 寛行

電子情報通信学会総合大会講演論文集 2000年.エレクトロニクス(2), 159, 2000-03-07  

0.5V単一電源動作を実現するための回路技術

岩田 徹 , 寺田 裕 , 赤松 寛範 , 松澤 昭 , 山内 寛行

電子情報通信学会技術研究報告. ED, 電子デバイス 97(106), 43-49, 1997-06-19  

0.5V単一電源動作を実現するための回路技術

岩田 徹 , 寺田 裕 , 赤松 寛範 , 松澤 昭 , 山内 寛行

電子情報通信学会技術研究報告. ICD, 集積回路 97(110), 43-49, 1997-06-19  

ED積を用いたGate-Over-diving CMOS Architectureの評価

寺田 裕 , 岩田 徹 , 山内 寛行 , 赤松 寛範 , 松沢 昭

電子情報通信学会総合大会講演論文集 1997年.エレクトロニクス(2), 154, 1997-03-06  

A Low Power Data Holding Circuit with an Intermittent Power Supply Scheme for sub-1V MT-CMOS LSIs

岩田　徹、赤松　寛範、平田　貴士、山本　浩郎山内　寛行、松澤　昭

IEICE ICD 1996, pp-17-24 

間欠的電源接続方式による1V動作のMTCMOSデータ保持回路

赤松 寛範 , 岩田 徹 , 山本 裕雄 , 平田 貴士 , 山内 寛行 , 小谷 久和 , 松澤 昭

電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス 96(226), 17-23, 1996-08-23  

0.8V/100MHz動作を実現するための低消費電力SRAMセルアーキテクチャーの提案

山内 寛行 , 岩田 徹 , 赤松 寛範 , 松沢 昭

電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス 96(226), 9-16, 1996-08-23  

超低保持電流DRAM回路技術 (特集/メモリデバイス) -- (半導体メモリ)

岩田 徹 , 山内 寛行 , 宇野 彰人

National technical report 41(6), 699-706, 1995-12  

Circuit Techniques for Super Low Retention Current DRAM

岩田　徹、山内　寛行

1995 IEICE ICD 1995, pp 1-7 

超低保持電流DRAMを実現するための回路技術

岩田 徹 , 山内 寛行

電子情報通信学会技術研究報告. ED, 電子デバイス 95(117), 1-7, 1995-06-23  

DRAMに何が要求されるか?--メモリカ-ドはSRAMからDRAMの時代へ (携帯情報端末をねらう次世代ロ-パワ-デバイス<特集>)

山内 寛行

エレクトロニクス 40(6), p30-33, 1995-06  

An Evaluation of Memory-Cell Leakage Current at 16Mbit DRAM

岩田　徹、山内　寛行、小谷　久和

IEICE Spring Conference C-637 1995, pp. 230 

超ロングリフレッシュDRAMを実現するための負電圧ワード線ドライバーの提案

山内 寛行 , 岩田 徹

電子情報通信学会総合大会講演論文集 1995年.エレクトロニクス(2), 231, 1995-03-27  

16MbitDRAMにおけるメモリセルリーク電流の評価

岩田 徹 , 山内 寛行 , 小谷 久和

電子情報通信学会総合大会講演論文集 1995年.エレクトロニクス(2), 230, 1995-03-27  

A Proposal of Negative-Biased Word-Line Driver Scheme for Ultra-Long Refresh DRAM

山内　寛行、岩田　徹

IEICE Spring Conference C-638 1995, pp. 231 

A Proposal of Charge-Recycling Bus Architecture for Local Data-Bus

山内　寛行、赤松　寛範、藤田　勉

IEICE Spring Conference C-521 1994, pp. 199 

An Ultra-Low Power Charge　Recycling Bus Architecture for Super High Data-Rate ULSI’s

山内　寛行、赤松　寛範、藤田　勉

IEICE ICD 1994, pp. 9-16 

ローカルデータバスに適した電荷再利用型バスアーキテクチャーの提案

山内 寛行 , 赤松 寛範 , 藤田 勉

電子情報通信学会秋季大会講演論文集 1994年.エレクトロニクス(2), 199, 1994-09-26  

超低消費電力で大容量転送レートを実現するULSIのための電荷再利用型バスアーキテクチャーの提案

山内 寛行 , 赤松 寛範 , 藤田 勉

電子情報通信学会技術研究報告. ICD, 集積回路 94(244), 9-16, 1994-09-22  

A Technique for Reducing of Input Capacitance with Localized Channel Stopper

辻　敏明、浅香　英雄、山内　寛行、藤田　勉

IEICE Spring Conference C-604 1994, pp. 172 

高速・低電圧16MビットCMOS DRAM (低消費電力半導体デバイス<特集>) -- (半導体デバイス)

山内 寛行 , 関口 満 , 谷口 隆

National technical report 39(6), p633-642, 1993-12  

A High　Speed Low Voltage　　Operated 16Mb CMOS DRAM

山内　寛行、鈴木　利一、澤田　昭弘、岩田　徹、辻　敏明、谷口　隆、福本　正紀、藤田　勉

IEICE ICD 1993, pp. 31-38 

高速・低電圧16M CMOS DRAM

山内 寛行 , 鈴木 利一 , 澤田 昭弘 , 岩田 徹 , 辻 敏明 , 谷口 隆 , 福本 正紀 , 藤田 勉

電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス 93(73), 31-38, 1993-05-27  

Parallel Column Access Redundancy Circuit

澤田　昭弘、菊川　博仁、山内　寛行、藤田　勉

IEICE Spring Conference C-644 1993, pp. 274 

An N&PMOS Cross-coupled Data-bus Amplifier for Realizing the High-speed and Low-power Operation

山内　寛行、澤田　昭弘、縣　政志、藤田　勉

IEICE Spring Conference C-635 1993, pp. 265 

A Design of Write Control Circuit for High speed DRAMs

岩田　徹、山内　寛行、藤田　勉

IEICE Spring Conference C-636 1993, pp. 266 

A Design of Write Control Circuit for High speed DRAMs

岩田　徹、山内　寛行、藤田　勉

IEICE Spring Conference C-636 1993, pp. 266 

Level Shift Circuit Reducing Power Consumption

鈴木　利一、柴山　晃徳、山内　寛行、藤田　勉

IEICE Spring Conference C-639 1993, pp. 269 

A Power Saving Techniques for Machine Learning Edge Computing: Toward an Era of AI Everywhere International conference

The 2nd International Conference on Electronics, Communications and Control Engineering (ICECC2019)  2019.4 

A Proposal of Low Power SRAM Cell Architecture for Realizing 0.8V/100Mhz Operation

山内　寛行、岩田　徹、赤松　寛範、松澤　昭

IEICE ICD 1996, pp-9-16 

A Deconvolution Error Avoidance Technique for Iterative Expectation–Maximization Algorithm International conference

International Conference on Computer Science and Engineering (ICCSE2019)  2019.2 

An overeview of How Should Tackle Various Energy Constraints for IoT Era International conference

Hynix seminor  2011.11 

Embedded SRAM Design

IEEE Asia Solid State Circuits Conference 2006  2006.11 

Embedded SRAM Circuit Design International conference

IEEE Advanced Circuit Technology Workshop in ISSCC2008  2008.2 

SRAM Variability Design International conference

Tutorial talk in ISSCC2009  2009.2 

Prospects for Variation Tolerant SRAM Circuit Designs International conference

IEEE ASICON  2009.11 

Variation Tolerant SRAM Circuit Design Trend in a Deeper Nanometer-Scale Technolog International conference

2009 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT2009)  2009.9 

Semiconductor integrated circuit apparatus and method of adjusting refresh timer cycle

Panasonic

수신기 및 신호 전송 시스템(Receiver and signal transmission system)

Hiroyuki Yamauchi

반도체집적회로장치및리프레시타이머주기조정방법(SEMICONDUCTOR INTEGRATED CIRCUIT AND ADJUSTMANT METHOD OF REFRESH TIMER)

Hiroyuki Yamauchi

옵셋 부설 비교장치 및 비교회로(OFFSETTING COMPARATOR DEVICE AND COMPARATOR CIRCUIT)

Hiroyuki Yamauchi

Semiconductor device having a plurality of semiconductor chips connected together by a bus

Akamatsu; Hironori , Iwata; Toru, Yamauchi; Hiroyuki

半導体記憶装置

Panasonic

半導体システム

Panasonic

Semiconductor memory device with a memory cell power supply circuit

Panasonic

Sense amplifier circuit

Panasonic

Semiconductor memory device having sub bit lines

Panasonic

Sensing circuit for a dynamic random access memory

Panasonic

Sense amplifier circuit for large-capacity semiconductor memory

Panasonic

Read circuit for large-scale dynamic random access memory

Panasonic

Semiconductor memory apparatus having reduced amount of bit line amplification delay

Panasonic

양방향 신호 전송 시스템(Bidirectional signal transmission system)

Hiroyuki Yamauchi

에스램 디바이스(SRAM device)

Hiroyuki Yamauchi

반도체기억장치(SEMICONDUCTOR MEMORY DEVICE)

Hiroyuki Yamauchi

정전류 출력회로(CONSTANT CURRENT OUTPUT CIRCUIT)

Hiroyuki Yamauchi

반도체 기억장치, 반도체 집적회로장치 및 휴대기기(SEMICONDUCTOR MEMORY DEVICE HAVING NORMAL AND STANDBYMODES, SEMICONDUCTOR INTEGRATED CIRCUIT AND MOBILEELECTRONIC UNIT)

Hiroyuki Yamauchi

감지증폭회로(SENSE AMPLIFIER CIRCUIT)

Hiroyuki Yamauchi

프로그램값 판정회로, 이것을 갖는 반도체 집적회로 장치및 프로그램값 판정방법(PROGRAM VALUE DETERMINATION CIRCUIT, SEMICONDUCTORINTEGRATED CIRCUIT DEVICE HAVING IT AND PROGRAM VALUEDETERMINATION METHOD)

Hiroyuki Yamauchi

반도체기억회로의 데이터유지시간 연장장치 및 연장방법(DEVICE AND METHOD FOR EXTENDING DATA HOLDING TIME OF MEMORY CIRCUIT)

Hiroyuki Yamauchi

구동기 회로, 수신기 회로 및 신호 송신 회로(Driver circuit, receiver circuit and signal transmitting circuit)

Hiroyuki Yamauchi

신호 전송 시스템(SIGNAL TRANSMISSION SYSTEM)

Hiroyuki Yamauchi

신호전송방법,신호전송회로및이것을이용한반도체집적회로(METHOD AND CIRCUIT FOR TRANSMITTING SIGNALS)

Hiroyuki Yamauchi

레벨변환회로,반도체집적회로및이들의제어방법(LEVEL CONVERTING CITCUIT IN SEMICONDUCTOR INTEGRATED CIRCUIT)

Hiroyuki Yamauchi

반도체집적회로(SEMICONDUCTOR INTEGRATED CIRCUIT)

Hiroyuki Yamauchi

Data transferring device

Hiroyuki Yamauchi

SRAM device

Hiroyuki Yamauchi

Semiconductor system

Hiroyuki Yamauchi

Semiconductor device and method for controlling the same

Hiroyuki Yamauchi

Data maintaining circuit

Hiroyuki Yamauchi

Signal transmission method, signal transmission circuit, and semiconductor integrated circuit using the same

Hiroyuki Yamauchi

Semiconductor memory device having normal and standby modes, semiconductor integrated circuit and mobile electronic unit

Hiroyuki Yamauchi

Determination circuit of program value, semiconductor integrated circuit device having the same and determination method of program value

Hiroyuki Yamauchi

SRAM device

Hiroyuki Yamauchi

반도체 집적회로 및 그 제어방법(SEMICONDUCTOR INTEGRATED CIRCUIT, AND CONTROL METHOD THEREOF)

Hiroyuki Yamauchi

신호 전송 방법(Signal transfer method)

Hiroyuki Yamauchi

신호 송ㆍ수신 장치 및 그 방법(Signal transmitting/receiving apparatus)

Hiroyuki Yamauchi

데이터 전송 장치(Data transmission device)

Hiroyuki Yamauchi

Semiconductor memory device

Hiroyuki Yamauchi

Method and circuit for transmitting signals and semiconductor integral circuit using same

Hiroyuki Yamauchi

Phase adjusting circuit, system including same and phase adjusting method

Hiroyuki Yamauchi

Semiconductor device and method for controlling the same

Hiroyuki Yamauchi

SRAM Devices

Hiroyuki Yamauchi

A semiconductor device having at least one symmetrical pair of MOSFETs

Hiroyuki Yamauchi

Signal transmission method, signal transmission circuit, and semiconductor integrated circuit using the same

Hiroyuki Yamauchi

Transmission system with differential data transmission

Hiroyuki Yamauchi

Data transfer device between computer nodes

Hiroyuki Yamauchi

Receiver and signal transmission system

Hiroyuki Yamauchi

DATA TRANSMITTER

Hiroyuki Yamauchi

Encoding of data for transmission over differential lines

Hiroyuki Yamauchi

Signal transmitting/receiving apparatus

Hiroyuki Yamauchi

差動信号判定回路および差動信号判定方法

松下電器

Static random access memory cell

Meng-Fan Chang, Lai-Fu Chen, Jui-Jen Wu, Hiroyuki Yamauchi

Static random access memory cell

Meng-Fan Chang, Lai-Fu Chen, Jui-Jen Wu, Hiroyuki Yamauchi

Static random access memory cell

Meng-Fan Chang, Lai-Fu Chen, Jui-Jen Wu, Hiroyuki Yamauchi

Static random access memory cell

Meng-Fan Chang, Lai-Fu Chen, Jui-Jen Wu, Hiroyuki Yamauchi

半導体記憶装置

山内寛行　山上由展

Static random access memory device

Ｈｉｒｏｙｕｋｉ　Ｙａｍａｕｃｈｉ

Charge redistribution circuit and method

Panasonic

Memory system with address conversion based on inherent performance condition

Panasonic

Sense amplifier circuit

Panasonic

Receiver and signal transmission system

Panasonic

Network unit with power saving mode inhibit based on interconnection relationship to neighboring nodes which is stored on the unit

Panasonic

SRAM device using MIS transistors

Panasonic

Data transferring device

Panasonic

Semiconductor memory device with a countermeasure to a signal delay

Panasonic

Programmed value determining circuit, semiconductor integrated circuit device including the same, and method for determining programmed value

Panasonic

Semiconductor SRAM having linear diffusion regions

Panasonic

Signal transmitting receiving apparatus

Panasonic

Semiconductor integrated circuit and method for fabricating the same

Panasonic

Semiconductor integrated circuit device and method for designing the same

Panasonic

Signal transmission system having multiple transmission modes

Panasonic

Signal transmission system having multiple transmission modes

Panasonic

Data transmission system

Panasonic

Data transmitter

Panasonic

Semiconductor memory device having normal and standby modes, semiconductor integrated circuit and mobile electronic unit

Panasonic

Offsetting comparator device and comparator circuit

Panasonic

Constant-current output circuit

Panasonic

Bidirectional signal transmission system

Panasonic

Address conversion circuit and address conversion system with redundancy decision circuitry

Panasonic

SRAM device

Panasonic

Variable delay circuit and phase adjustment circuit

Panasonic

Method for fabricating semiconductor device

Panasonic

Voltage control circuit network device and method of detecting voltage

Panasonic

Signal transmission driver circuit, receiver circuit, and method thereof for transmitting and receiving information based on multiple periods and/or a delay function

Panasonic

Semiconductor memory

Panasonic

Signal transmitting circuit, signal receiving circuit, signal transmitting/receiving circuit, signal transmitting method, signal transmitting/receiving method, semiconductor integrated circuit, and control method thereof

Panasonic

Signal transmitting circuit, signal receiving circuit, signal transmitting/receiving circuit, signal transmitting method, signal receiving method, signal transmitting/receiving method, semiconductor integrated circuit, and control method thereof

Panasonic

Signal transmitting circuit and method with selection among differential pairs

Panasonic

Transmission circuit and reception circuit

Panasonic

Memory access buffer and reordering apparatus using priorities

Panasonic

Operation timing controllable system

Panasonic

Semiconductor device capable of cutting off a leakage current in a defective array section

Panasonic

Signal transmitting circuit, signal receiving circuit, signal transmitting/receiving circuit, signal transmitting method, signal receiving method, signal transmitting/receiving method, semiconductor integrated circuit, and control method thereof

Panasonic

Semiconductor device capable of cutting off a leakage current in a defective array section and method thereof

Panasonic

Signal transfer method

Panasonic

Circuit and method for determining level of differential signal

Panasonic

Apparatus and method for extending data retention time of semiconductor storage circuit

Panasonic

Semiconductor integrated circuit device

Panasonic

Semiconductor memory devices

Panasonic

Level-shifter, semiconductor integrated circuit, and control methods thereof

Panasonic

Static random access memory having variable supply voltages to the memory cells and method of operating thereof

Panasonic

Semiconductor memory device having minimal leakage current

Panasonic

Data holding circuit

Panasonic

Low voltage, low power operable static random access memory device

Panasonic

Monolithic image data memory system and access method that utilizes multiple banks to hide precharge time

Panasonic

Phase adjusting circuit, system including the same and phase adjusting method

Panasonic

Circuit and method for signal processing

Panasonic

Circuit and method for signal transmission

Panasonic

Signal transmitting circuit, signal receiving circuit, signal transmitting/receiving circuit, signal transmitting method, signal receiving method signal transmitting/receiving method, semiconductor integrated circuit, and control method thereof

Panasonic

Dynamic random access memory

Panasonic

Reading circuit for semiconductor memory

Panasonic

Read circuit of dynamic random access memory

Panasonic

Read/write circuit including sense amplifiers for use in a dynamic RAM

Panasonic

Semiconductor device having at least one symmetrical pair of MOSFETs

Panasonic

Differential transmission circuit

Panasonic

Circuit redundancy having a variable impedance circuit

Panasonic

Semiconductor integrated circuit

Panasonic

Level-shifter, semiconductor integrated circuit, and control methods thereof

Panasonic

Semiconductor memory device having a plurality of blocks

Panasonic

SRAM device

Panasonic

信号伝送回路及び信号伝送方法

松下電器

半導体集積回路装置

松下電器

信号伝送システム

松下電器

ドライバ回路、レシーバ回路および信号伝送回路

松下電器

電圧制御回路、ネットワーク機器および電圧検知方法

松下電器

ワードドライバ回路

松下電器

位相調整回路を含むシステムおよび位相調整方法

松下電器

ＳＲＡＭ装置

松下電器

定電流出力回路

松下電器

送信回路及び受信回路

松下電器

半導体集積回路

松下電器

差動伝送回路

松下電器

省電力ネットワーク装置

松下電器

出力バッファ回路

松下電器

信号伝送回路及び信号伝送方法

松下電器

半導体集積回路

松下電器

半導体集積回路

松下電器

半導体記憶回路のデータ保持時間の延長装置及び延長方法

松下電器

画像データメモリ

松下電器

データ保持回路

松下電器

半導体集積回路

松下電器

半導体集積回路装置

松下電器

半導体集積回路

松下電器

複数アドレス保持記憶装置

松下電器

半導体メモリの冗長回路

松下電器

半導体装置および半導体装置を制御する方法

松下電器

半導体集積回路

松下電器

半導体集積回路

松下電器

半導体メモリの読み出し回路

松下電器

信号電位変換回路

松下電器

半導体記憶装置

松下電器

ダイナミックＲＡＭ

松下電器

半導体集積回路装置及びリフレッシュタイマー周期調整方法

松下電器

半導体記憶装置

松下電器

ダイナミックＲＡＭの読み出し回路

松下電器

Semiconductor integrated circuit device and method for designing the same

Panasonic

Semiconductor integrated circuit device and method for manufacturing the same

Panasonic

ダイナミックＲＡＭの読み出し方法

松下電器

センスアップ回路

松下電器

ダイナミックＲＡＭの読み出し回路

松下電器

半導体装置

松下電器

ダイナミックＲＡＭ

松下電器

半導体メモリの読み出し回路

松下電器

ダイナミックＲＡＭの読み出し回路

松下電器

センスアンプ回路

松下電器

信号伝送方法

松下電器

ダイナミックＲＡＭの読み出し回路

松下電器

半導体記憶装置

松下電器

Method of fabricating semiconductor integrated circuit device

Panasonic

Sense amplifier circuit

Panasonic

Semiconductor memory device

Panasonic

Semiconductor integrated circuit device and method for designing the same

Panasonic

SIGNAL TRANSMITTING CIRCUIT, SIGNAL RECEIVING CIRCUIT, SIGNAL TRANSMITTING/RECEIVING CIRCUIT, SIGNAL TRANSMITTING METHOD, SIGNAL RECEIVING METHOD, SIGNAL TRANSMITTING/RECEIVING METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT, AND CONTROL METHOD THEREOF

Panasonic

6,898,111

Panasonic

Signal transmitting receiving apparatus

Panasonic

Signal transmitting receiving apparatus

Panasonic

Semiconductor integrated circuit and method for fabricating the same

Panasonic

Clock recovery circuit

Panasonic

Memory system

Panasonic

Semiconductor system having a source potential supply section

Panasonic

Mask ROM

Panasonic

半導体メモリ

松下電器

ＲＡＭの読み出し回路

松下電器

ダイナミックＲＡＭの読み出し回路

松下電器

レベル変換回路、半導体集積回路及びこれ等の制御方法

松下電器

受信装置および信号伝送システム

松下電器

信号伝送方法

松下電器

半導体装置

松下電器

半導体メモリ装置及び半導体集積回路

松下電器

メモリシステム

松下電器

動作タイミング制御機能を有するシステム

松下電器

半導体集積回路装置およびその製造方法

Panasonic

半導体集積回路とその製造方法

Panasonic

ＳＲＡＭ装置

Panasonic

センスアンプ回路

松下電器

信号伝送回路、信号受信回路及び送受信回路、信号伝送方法、信号受信方法及び信号送受信方法、並びに半導体集積回路及びその制御方法

松下電器

データ伝送装置

松下電器

データ伝送システム

松下電器

信号送受信装置

松下電器

半導体集積回路装置およびそのデータ入出力部

松下電器

ＳＲＡＭ装置

松下電器

オフセット付きコンパレータ装置、およびコンパレータ回路

松下電器

位相調整回路

松下電器

半導体集積回路及び半導体集積回路システム

松下電器

クロックリカバリ回路

松下電器

ＳＲＡＭ装置

松下電器

半導体記憶装置

松下電器

出力バッファ回路

松下電器

半導体集積回路

松下電器

半導体集積回路

松下電器

ICNCS2014 Excellent Oral Presentation Award

2014.3  

ICEET 2013 Best Presentation Award

2013.4  

ICNCS 2013 Best Presentation Award

2013.4  

A Reduction Technique for Temporal-Spatial Vth Variations and Leakage in a Coordinated Manner for SRAM-ReRAM Stacked Memories

Grant number：26420326  2014.4 - 2017.3

Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Scientific Research (C)

半導体集積回路上に実現するSRAMの高度化技術に関する研究奨励

2014.4 - 2015.3

株式会社ロジック・リサーチ  奨学寄付金 

山内　寛行

LSI設計におけるプロセスばらつきの検討及びその技術的コンサルティング

2013.4 - 2017.3

シリコンライブラリ株式会社  奨学寄付金 

山内　寛行

LSI設計におけるプロセスばらつきの検討及びその技術的コンサルティング

2011.4 - 2012.3

シリコンライブラリ株式会社  奨学寄付金 

山内　寛行

Study on Design Methodology for Reducing Both of Spatial and Temoporal Random Threshold Variation Based on Potential Control of SRAM Cell Terminals

Grant number：23560424  2011 - 2013

Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Scientific Research (C)

STARC協力講座

2010

STARC  奨学寄付金 

STARC協力講座

2009

STARC  奨学寄付金 

SRAM Design

2009

パナソニック  受託研究 

STARC協力講座

2008

STARC  奨学寄付金 

SRAM Design

2006.12 - 2007.11

パナソニック  受託研究 

VLSI 設計研究システム

2006

その他補助金  平成18年度文科省施設・整備補助事業

2023   Graduation Study

2023   Training for International Conference

2023   Seminar in Intelligent System

2023   Advanced Intelligent System

2023   Research Study for Master's Thesis in

2022   Seminar on Fundamentals of Computer

2022   Logic Design

2022   System LSI

2022   Experiments of Computer Science and

2022   Graduation Study

2022   Training for International Conference

2022   Advanced Intelligent System

2022   Seminar in Intelligent System

2022   Research Study for Master's Thesis in

2021   Seminar on Fundamentals of Computer

2021   Logic Design

2021   System LSI

2021   Experiments of Computer Science and

2021   Special Lectures in Computer Science and

2021   Graduation Study

2021   Advanced Intelligent System

2021   Training for International Conference

2021   Seminar in Intelligent System

2021   Research Study for Master's Thesis in

2020   Seminar on Fundamentals of Computer

2020   Logic Design

2020   System LSI

2020   Experiments of Computer Science and

2020   Special Lectures in Computer Science and

2020   Graduation Study

2020   Advanced Intelligent System

2020   Seminar in Intelligent System

2020   Training for International Conference

2020   Research Study for Master's Thesis in

2020   Intelligence Information Engineering

2019   Seminar on Fundamentals of Computer

2019   Logic Design

2019   System LSI

2019   Experiments of Computer Science and

2019   Special Lectures in Computer Science and

2019   Graduation Study

2019   Advanced Intelligent System

2019   Training for International Conference

2019   Seminar in Intelligent System

2019   Research Study for Master's Thesis in

2019   Intelligence Information Engineering

2018   Seminar on Fundamentals of Computer

2018   Logic Design

2018   Experiments of Computer Science and

2018   Special Lectures in Computer Science and

2018   System LSI

2018   Graduation Study

2018   Training for International Conference

2018   Seminar in Intelligent System

2018   Advanced Intelligent System

2018   Research Study for Master's Thesis in

2018   Special Seminar in Intelligent

2017   Seminar on Fundamentals of Computer

2017   Logic Design

2017   VLSI Design

2017   Experiments of Computer Science and

2017   Graduation Study

2017   Training for International Conference

2017   Seminar in Intelligent System

2017   Advanced Intelligent System

2017   Research Study for Master's Thesis in

2016   Seminar on Fundamentals of Computer

2016   Internship

2016   Logic Design

2016   Experiments of Computer Science and

2016   Special Lectures in Computer Science and

2016   VLSI Design

2016   Graduation Study

2016   Training for International Conference

2016   Seminar in Intelligent System

2016   Advanced Intelligent System

2016   Special Research

IEEE ASSCC Program Committee

2010

2010-2012 （独）新エネルギー・産業技術総合開発機構（NEDO）プロジェクト審査委員

2010

2010-2012 IEICE ICDメモリ委員会委員

2010

IEEE Symposium on VLSI Circuit Program Committee 2008-2009

2009

IEEE ASSCC Program Committee 2008-2009

2009

IEICE ICD TPC　Member

2009

IEEE International ＭＴＤＴ Program committee 2007,2009

IEEE International Solid-State Circuits Conference Program committee 2002-2010

IEEE ISSCC Program Committee Member