Updated on 2024/12/05
博士（工学）
超伝導回路
単一磁束量子デバイス
集積回路工学
ニューラルネットワーク
ジョセフソン素子
Superconducting circuit
Integrated circuit
人工神経回路
超伝導
Others / Others / electronic equipment
Others / Others / Electronic device
Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Electron device and electronic equipment
東北大学大学院 工学研究科 電気・通信工学専攻 後期3年の課程修了
Tohoku University
2015年4月～ 福岡工業大学
1998年4月～2015年3月 東北大学電気通信研究所
電子情報通信学会
応用物理学会
Random Number Generation Utilizing Timing Jitters of Single-Flux-Quantum Propagation Reviewed
Y. Mizugaki, K. Sato, H. Shimada, T. Onomi
Proceedings of 2023 Photonics and Electromagnetics Research Symposium 1744 - 1748 2023.7
Evaluation of a True Random Number Generator Utilizing Timing Jitters in RSFQ Logic Circuits Reviewed
K. Sato, N. Sega, Y. Somei, H. Shimada, T. Onomi, Y. Mizugaki
IEICE Transactions on Electronics E105-C ( 6 ) 296 - 299 2022.6
Hardware Random Number Generator Using Josephson Oscillation and SFQ Logic Circuits Reviewed
Takeshi Onomi and Yoshinao Mizugaki
IEEE Transactions on Applied Superconductivity 30 ( 7 ) 1301305 2020.10
“Design of a Hardware Random Number Generator using Josephson Oscillation and SFQ Logic Circuits”
T. Onomi
Abstracts of 2019 IEEE International Superconductive Electronics Conference 3-PS-P-8 2019.7
“Performance Analysis of Relaxation Oscillator Using Superconducting Schmitt Trigger Inverter Based on Coupled SQUIDs Gate”
T. Onomi
Abstracｔs of 2016 Applied Superconductivity Conference 4EPoE-06 2016.9
Experimental demonstration and performance estimation of a new relaxation oscillator using a superconducting Schmitt trigger Reviewed
T. Onomi
Physics Procedia 81 141 - 144 2016.5
“Implementation of a New Relaxation Oscillator Using Superconducting Schmitt Trigger Inverter”
T. Onomi
Proceedings of the 2015 IEEE 15th International Superconductive Electronics Conference DS-P20 2015.7
“Performance analysis of Bidirectional Associative Memories by using the Inverse Function Delayless model”
C. Bao, T. Onomi, Y. Hayakawa, S. Sato, and K. Nakajima
Proceedings of 2014 International Symposium on Nonlinear Theory and Its Applications 516 - 519 2014.9
“Relaxation Oscillator Using Superconducting Schmitt Trigger Inverter”
T. Onomi
Proceedings of 2014 International Symposium on Nonlinear Theory and Its Applications 284 - 287 2014.9
“Back Propagation Learning Based on an IDL Model”
Y. Horiuchi, Y. Hayakawa, T. Onomi, and K. Nakajima
Proceedings of 2014 International Symposium on Nonlinear Theory and Its Applications 512 - 515 2014.9
“An improved superconducting neural circuit and its application for a neural network solving a combinatorial optimization problem” Reviewed
T. Onomi, and K. Nakajima
Journal of Physics: Conference Series 507 42029 2014.6
“Basic Technology of Integrated Systems for Artificial Neural Networks”
T. Onomi, and K. Nakajima
Abstracts of the 1st International Symposium on Brainware LSI 12 2014.3
“Neuron Circuit using Coupled SQUIDs Gate with Flat Output Characteristics for Superconducting Neural Network” Reviewed
T. Onomi, and K. Nakajima
IEICE Trans. Electron. E97-C ( 3 ) 173 - 177 2014.3
“High-speed single flux quantum parallel multiplier using Dadda type partial product addition”
A. Yamada, T. Onomi, and K. Nakajima
7th International WorkShop on New Group IV Semiconductor Nanoelectronics?and?JSPS Core-to-Core Program Joint Seminar?Atomically Controlled Processing for Ultralarge Scale Integration" P-16 2014.1
“Characteristics of rf-SQUID Ladder Circuits”
Y. Tsuji, T. Onomi, and K. Nakajima
Proceedings of Superconducting SFQ VLSI Workshop SSV 2013 60 - 63 2013.11
“Comparative Study of SFQ Parallel Multipliers”
A. Yamada, T. Onomi, and K. Nakajima
Proceedings of Superconducting SFQ VLSI Workshop SSV 2013 78 - 81 2013.11
“An improved superconducting neural circuit and its application for a neural network solving a combinatorial optimization problem”
T. Onomi, and K. Nakajima
8th European Conf. on Applied Superconductivity 3P-EL1-16 2013.9
“Design and Fabrication of an Improved Neural Circuit for Superconducting Neural Network Solving a Combinatorial Optimization Problem”
T. Onomi and K. Nakajima
Proceedings of Superconducting SFQ VLSI Workshop SSV 2012 63 - 66 2012.12
“Collective Switching Characteristics of Josephson Junctions”
H. Katayama, R. Nakamoto, K. Inomata, T. Onomi, S. Sato, and K. Nakajima
Proceedings of Superconducting SFQ VLSI Workshop SSV 2011 56 - 57 2011.11
“4-bit SFQ Multiplier Based on Booth Encoder” Reviewed
R. Nakamoto, S. Sakuraba, T. Onomi, S. Sato, and K. Nakajima
IEEE Trans. Applied Superconductivity 21 ( 3 ) 852 - 855 2011.6
“Superconducting Neural Network for Solving a Combinatorial Optimization Problem” Reviewed
T. Onomi, Y.Maenami, and K.Nakajima
IEEE Trans. Applied Superconductivity 21 ( 3 ) 701 - 704 2011.6
“High Throughput Parallel Arithmetic Circuits for Fast Fourier Transform” Reviewed
R. Nakamoto, S. Sakuraba, A. Martins, T. Onomi, S. Sato, and K. Nakajima
IEICE Trans. Electron., E94-C ( 3 ) 280 - 287 2011.3
“High Throughput Parallel Multiplier of SFQ Circuits based on the Booth Encoder,”
R. Nakamoto, S. Sakuraba, T. Onomi, S. Sato, and K. Nakajima
Proceedings of the 3rd Student Organizing International Mini-Conf. on Information Electronics Systems 172 - 173 2010.10
“Superconducting Neural Network Solving a Combinatorial Optimization Problem”
T. Onomi, Y.Maenami, and K.Nakajima
2010 Applied Superconductivity Conference 3EP3B-04 2010.8
“4-bit SFQ Multiplier Based on Booth Encoder”
R. Nakamoto, S. Sakuraba, T. Onomi, S. Sato, and K. Nakajima
2010 Applied Superconductivity Conference 4EPA-07 2010.8
“Booth encoder for large scale integration SFQ circuits”
R. Nakamoto, S. Sakuraba, T. Onomi, S. Sato, and K. Nakajima
Proceedings of Superconducting SFQ VLSI Workshop SSV 2010 103 - 104 2010.1
“High Throughput Parallel Arithmetic Circuits for Fast Fourier Transform”
S. Sakuraba, A. Martins, T. Onomi, S. Sato, and K. Nakajima
Proceedings of Superconducting SFQ VLSI Workshop SSV 2010 10月15日 2010.1
“4-bit Parallel Adder for a Fast Fourier Transform System”
S. Sakuraba, T. Onomi, and K. Nakajim
Proceedings of Superconducting SFQ VLSI Workshop SSV 2009 P12 2009.6
“Implementation of High-Speed Single Flux-Quantum Up/Down Counter for the Neural Computation Using Stochastic Logic” Reviewed
T. Onomi, T. Kondo, and K. Nakajima
IEEE Trans. Applied Superconductivity 19 ( 3 ) 626 - 629 2009.6
“4-bit Parallel Multiplier for a Fast Fourier Transform”
S. Sakuraba, T. Onomi, and K. Nakajima
Abstracts of the 12th International Superconductive Electronics Conf. SP-P40 2009.6
“Implementation of high-speed single flux-quantum up/down counter for the neural computation using stochastic logic”
T. Onomi and K. Nakajima
2008 Applied Superconductivity Conf. 3EPC05 2008.8
“High-speed single flux-quantum up/down counter for neural computation using stochastic logic” Reviewed
T. Onomi, T. Kondo, and K. Nakajima
Journal of Physics: Conference Series 97 12187 2008.3
“SFQ Parallel Multiplier, Adder, and Subtractor”
S. Sakuraba, A. Martins, T. Onomi and K. Nakajima
Proceedings of Superconducting SFQ VLSI Workshop SSV 2008 P2-14 2008.1
“Integrated Multiplier for Fast Fourier Transform System Using Single Flux Quantum Data Processing Circuits,”
K. Nakajima, A. Martins, S. Sakuraba, and T. Onomi
Proceedings of Superconducting SFQ VLSI Workshop SSV 2008 26 - 27 2008.1
“High-speed single flux-quantum up/down counter for neural computation using stochastic logic”
T. Onomi, K. Kondo, and K. Nakajima
Abstracts of 8th European Conference on Applied Superconductivity S5-0346 2007.9
“Design and Implementation of Stochastic Neurosystem Using SFQ Logic Circuits” Reviewed
T. Kondo, M. Kobori, T. Onomi, and K. Nakajima
IEEE Trans. Applied Superconductivity 15 ( 2 ) 320 - 323 2005.6
“Superconducting neural circuits using stochastic logic and new fabrication process elements”
T. Onomi, T. Kondo, T. Yamamae, and K. Nakajima
Proceedings of 2005 Japan-Taiwan Symposium on Superconductive Electronics 119 - 122 2005.2
“Design and Implementation of Stochastic Neurosystem Using SFQ Logic Circuits”
T. Kondo, M. Kobori, T. Onomi, and K. Nakajima
2004 Applied Superconductivity Conference 2EK03 2004.9
“Design and fabrication of superconducting microstrip lines using Nb2O5 insulator”
T. Yamamae, T. Onomi, and K. Nakajima
2004 Applied Superconductivity Conference 3EF11 2004.9
“Observation of the Emission from Bi-2212 Intrinsic Junctions in the Flux-flow State by Nb/AlOx/Nb Junction”
Y. Yamada, K. Nakajima, J. Chen, T. Onomi, Koji Nakajima, and T. Yamashita
Abstracts of Second East Asia Symposium on Superconductive Electronics 63 2003.11
“Design and Implementation of the Parallel Multiplier using SFQ”
I. Shimizu, Y. Horima, T. Onomi and K. Nakajima
Extended Abstracts of 9th International Superconductive Electronics Conf. PMo-29 2003.7
“Design of component circuits for fast Fourier transform based on SFQ logic”
M. Kobori, Y. Horima, T. Onomi and K. Nakajima
Extended Abstracts of 9th International Superconductive Electronics Conf. PMo-23 2003.7
“Improved design for Parallel Multiplier based on Phase-Mode Logic” Reviewed
Y. Horima, T. Onomi, M. Kobori, I. Shimizu, and K. Nakajima
IEEE Transactions on Applied Superconductivity 13 ( 2 ) 527 - 530 2003.6
“Implementation of Phase-Mode Arithmetic Elements for Parallel Signal Processing” Reviewed
T. Onomi, Y. Horima, M. Kobori, I. Shimizu and K. Nakajima
IEEE Transactions on Applied Superconductivity 13 ( 2 ) 583 - 586 2003.6
“Comparison between an AND Array and a Booth Encoder for Large-Scale Phase-Mode Multipliers” Reviewed
Y. Horima, I. Shimizu, M. Kobori, T. Onomi, and K. Nakajima
IEICE Trans. Electronics E86-C ( 1 ) 16 - 23 2003.1
“Implementation of Phase-Mode Arithmetic Elements for Parallel Signal Processing”
T. Onomi, Y.Horima, M.Kobori and K. Nakajima
Abstracts of Applied Superconductivity Conf. 2002 4EC02 2002.8
“Optimization of Multiplier with Phase-Mode Logic Family”
Y. Horima, T. Onomi, M. Kobori, I. Shimizu and K. Nakajima
Abstracts of Applied Superconductivity Conf. 2002 4EC07 2002.8
“Design of Phase-Mode Pipelined Parallel Multiplier”
Y. Horima, M. Seki, T. Onomi, and K. Nakajima
Extended Abstracts of 8th International Superconductive Electronics Conference 179 - 180 2001.6
“Phase-Mode Pipelined Parallel Multiplier” Reviewed
T. Onomi, K. Yanagisawa, M. Seki, and K. Nakajima
IEEE Trans. on Applied Superconductivity 11 ( 1 ) 541 - 544 2001.3
“New Phase-Mode Logic Gates with Large Operating Regions of Circuit Parameters” Reviewed
T. Onomi, K. Yanagisawa, and K. Nakajima
IEEE Trans. on Applied Superconductivity 11 ( 1 ) 974 - 977 2001.3
“New phase-mode logic gates with large operating regions of circuit parameters”
T. Onomi, K. Yanagisawa and K. Nakajima
Pre-Conference Booklet of Applied Superconductivity Conference 2000 101 2000.9
“Phase-mode pipelined parallel multiplier”
K. Yanagisawa, M. Seki, T. Onomi, and K. Nakajima
Pre-Conference Booklet of Applied Superconductivity Conference 2000 81 2000.9
“Magnetic Isolation on a Superconducting Ground Plane” Reviewed
Y. Mizugaki, K. Yanagisawa, T. Onomi, T. Yamashita, K. Nakajima
Japanese Journal of Applied Physics 38 ( 10 ) 5869 - 5870 1999.10
“New fabrication process elements of Phase-Mode Logic Circuits” Reviewed
T. Onomi and K. Nakajima
IEEE Transactions on Applied Superconductivity 9 ( 2 ) 3318 - 3321 1999.6
“Fluxoid-type Logic Circuits” Reviewed
K. Nakajima, Y. Mizugaki, T. Onomi, and T. Yamashita
Physics and Applications of Mesoscopic Josephson Junctions, The Physical Society of Japan 267 - 288 1999.5
“Phase-Mode Circuits for High-Performance Logic” Reviewed
T. Onomi, Y. Mizugaki, H. Satoh, T. Yamashita and K. Nakajima
IEICE Trans. on Electronics E81-C ( 10 ) 1608 - 1617 1998.10
“Digital circuits based on single flux quanta”
K. Nakajima and T. Onomi
Abstracts of the 1998 Int. Conf. on Solid State Devices and Materials 372 - 373 1998.9
“Implementation of phase-mode logic circuits based on new integration design”
T. Onomi, Y. Mizugaki, K. Nakajima, and T. Yamashita
Abstracts of 1998 Applied Superconductivity conference ASC'98 89 1998.9
“Characterization of the fluxoid Josephson transmission line and the application to phase-mode circuits”
T. Onomi, T. Yamashita, Y. Mizugaki, and K. Nakajima
Extended Abstracts, 6th Int. Superconductive Electronics Conference ISEC'97 296 - 298 1997.6
“Design and Fabrication of an Adder Circuit in the Extended Phase-Mode Logic” Reviewed
T. Onomi, T. Yamashita, Y. Mizugaki, and K. Nakajima
IEEE Trans. Appl. Superconduct. 7 ( 2 ) 3172 - 3175 1997.6
“Phase Mode Logic and High Jc Junctions”
K. Nakajima, Y. Mizugaki, T. Onomi, and T. Yamashita
Extended Abstracts of the 5th Int. Workshop on High-Temperature Superconducting Electron Devices 49 - 50 1997.5
“Fluxoid-type Logic Circuits”
K. Nakajima, Y. Mizugaki, T. Onomi, and T. Yamashita
The CRL Int. Symposium Physics and Applications of Mesoscopic Josephson Junctions 35 - 36 1997.3
“Binary Counter with New Interface Circuits in the Extended Phase-Mode Logic Family” Reviewed
T. Onomi, Y. Mizugaki, T. Yamashita, and K. Nakajima
IEICE Trans. on Electronics E79-C 1200 - 1205 1996.9
“Design and Fabrication of an Adder Circuit in the Extended Phase-Mode Logic”
T. Onomi, T. Yamashita, Y. Mizugaki, and K. Nakajima
1996 Applied Superconductivity Conference EMA-6 1996.8
“Experimental operation of an RS flip-flop composed of nonlatching Josephson gates” Reviewed
Y. Mizugaki, T. Onomi, K. Nakajima, and T. Yamashita
IEEE Trans. on Applied Superconductivity 6 ( 2 ) 90 - 93 1996.6
“Superconducting Phase-Mode Logic Circuit Using Resistive Ground Contact”
T. Onomi, Y. Mizugaki, K. Nakajima, and T. Yamashita
International Workshop on Quantum Mechanical Computer 1995.12
“Experimental Realization of Extended Phase-Mode Logic Elements”
T. Onomi, Y. Mizugaki, K. Nakajima, and T. Yamashita
Extended Abstracts of 5th International Superconductive Electronics Conference 195 - 197 1995.9
“Extended Phase-Mode Logic-Circuits with Resistive Ground Contact” Reviewed
T. Onomi, Y. Mizugaki, K. Nakajima, and T. Yamashita
IEEE Trans. on Applied Superconductivity 5 ( 3 ) 3464 - 3471 1995.5
“Extended Phase Mode Logic Circuits”
K. Nakajima, T. Onomi, T. Yamashita, and Y. Sawada
Proceeding of 1993 International Symposium on Nonlinear Theory and Its Applications 2 749 - 754 1993.12
単一磁束量子回路による発振パルスサンプリング型真性乱数生成器の開発
小野美武
電子情報通信学会超伝導エレクトロニクス研究会
単一磁束量子発振器に基づく超伝導乱数生成器の乱数品質とANDゲートのスイッチング時間の関係
古賀仁誌、小野美武
2020年応用物理学会九州支部講演会
単一磁束量子発振器に基づく超伝導乱数生成器の乱数品質の検証
小野美武
2019年応用物理学会九州支部学術講演会
SFQ パルス発振器に基づくSFQ 乱数生成器の試作
小野美武、水柿義直
2019 年電子情報通信学会エレクトロニクスソサイエティ大会
結合SQUIDs ゲートを利用したシュミットトリガー回路による弛張発振器の発振周波数と回路パラ メータの関係
小野美武
2018年応用物理学会九州支部学術講演会
結合SQUIDs ゲートのしきい値ゆらぎと入力電流掃引速度の関係
小野美武
2017年応用物理学会九州支部学術講演会
結合SQUIDs ゲートの閾値ゆらぎのマッカンバパラメータ依存性
小野美武、重枝柊弥
2017 年電子情報通信学会エレクトロニクスソサイエティ大会
超伝導シュミットトリガーインバータによる弛張発振器の動作検証
小野美 武
電子情報通信学会超伝導エレクトロニクス研究会
配線包囲型構造による超伝導マイクロストリップライン間の磁気結合度の評価
小野美 武、中島 康治
第62回応用物理学会春季学術講演会
2023 Logic Circuits
2023 Electric Circuits Ⅲ
2023 Information Electronics Laboratory
2023 Information Electronics Laboratory
2023 Graduation Study
2023 Advanced Lectures on Electronic
2023 Seminar in Information Electronics
2022 Logic Circuits
2022 Electric Circuits Ⅲ
2022 Information Electronics Laboratory
2022 Information Electronics Laboratory
2022 Graduation Study
2022 Advanced Lectures on Electronic
2022 Seminar in Information Electronics
2022 Research Study for Master's Thesis in
2021 Logic Circuits
2021 Information Electronics Laboratory
2021 Electric Circuits Ⅲ
2021 Information Electronics Laboratory
2021 Graduation Study
2021 Advanced Lectures on Electronic
2021 Seminar in Information Electronics
2021 Research Study for Master's Thesis in
2020 Logic Circuits
2020 Electric Circuits Ⅲ
2020 Information Electronics Laboratory
2020 Information Electronics Laboratory
2020 Graduation Study
2020 Advanced Lectures on Electronic
2020 Seminar in Information Electronics
2019 Logic Circuits
2019 Electric Circuits Ⅲ
2019 Information Electronics Laboratory
2019 Information Electronics Laboratory
2019 Graduation Study
2019 Advanced Lectures on Electronic
2019 Seminar in Information Electronics
2018 Logic Circuits
2018 Electric Circuits Ⅲ
2018 Information Electronics Laboratory
2018 Information Electronics Laboratory
2018 Graduation Study
2018 Seminar in Information Electronics
2018 Advanced Lectures on Electronic
2017 Logic Circuits
2017 Informatin Electronics Laboratory
2017 Electric Circuits III
2017 Informatin Electronics Laboratory
2017 Graduation Study
2017 Seminar in Information Electronics
2017 Advanced Lectures on Electronic
2016 Logic Circuits
2016 Electric Circuits III
2016 Informatin Electronics Laboratory
2016 Informatin Electronics Laboratory
2016 Graduation Study
2016 Advanced Lectures on Electronic
2016 Seminar in Information Electronics
Citation count denotes the number of citations in papers published for a particular year.